1. Field of the Invention
This invention relates to electronic information storage devices containing bistable semiconductor memory cells.
2. Prior Art
Cellular electronic information storage devices operable in both the read mode and the write mode may be generally divided into two categories: static memories and dynamic memories. In a static memory consisting of one or more multistable static memory cells, data entered into the static memory does not degrade significantly with time. As long as power is supplied to the static memory, the information in the static memory cells remains essentially indefinitely or until a new pattern of information is written in. Conversely, in a dynamic memory consisting of one or more dynamic memory cells, the information entered into the dynamic memory does degrade with time. The dynamic memory must be periodically refreshed to maintain the data.
An electronic static memory cell in the prior art typically consists of a pair of cross-coupled transistor inverter stages and a load circuit arranged in a bistable configuration. The inverter stages are usually either a pair of bipolar transistors or a pair of metal-oxide semiconductor (M0S) field-effect transistors. The load devices for a static memory cell conventionally consists of two or more transistors and/or resistors. Prior art static memory cells are illustrated by R. G. Hibberd in Integrated Circuits, A Basic Course for Engineers and Technicians (McGraw-Hill Book Co., 1969), Lesson 4, Pages 63-68.
A disadvantage of the cross coupling in prior art static memory cells is that the cells occupy a relatively large amount of space on a semiconductor chip because many elements are utilized in each cell.
Under current five-micron design rules, a typical cross-coupled static memory cell occupies about 3.0 square mils; for a 4096-bit static memory, the total required chip space is approximately 20,000 square mils. Under upcoming three-micron design rules, a 4096-bit memory employing cross-coupled static memory cells would occupy about 7,000 square mils.
Conventional dynamic memories include MOS dynamic memories, charge-coupled devices, and bipolar integrated injection logic (I.sup.2 L) dynamic memories. Each cell in a typical MOS dynamic memory includes a storage capacitor for storing a data bit and an MOS field-effect transistor for accessing the storage capacitor. Each cell in a bipolar I.sup.2 L dynamic memory has one bipolar transistor for storing a data bit and another bipolar transistor for supplying the stored charge.
In the prior art, dynamic memory cells usually require fewer elements than static memory cells and thus occupy less chip space. Dynamic memories also normally require less power to operate than static memories.
A disadvantage of dynamic memories is that a substantial amount of complex peripheral circuitry must be employed for periodically refreshing the memory cells. Dynamic memories within the prior art are thus harder to implement. Additionally, static memories are less noise sensitive and generally have shorter cycle times than dynamic memories.
One technique for reducing memory cell size is to merge some of the cell elements with one another. In the prior art bipolar static I.sup.2 L technology, where the load circuit consists of at least two bipolar transistors, each of the cross-coupled inverter-stage transistors is merged with a corresponding load transistor. The inverter-stage transistor is of one type--for example, a PNP transistor--and the load transistor is of the opposite type--for example, an NPN transistor. Prior art dynamic memory cells employing merged elements include bipolar I.sup.2 L memory cells in which the storage transistor is of one type--for example, an NPN transistor--and the transistor which supplies the stored charge is of the opposite type--for example, a PNP transistor. W. B. Sander, J. M. Early, and T. A. Longo, "A 4096.times.1 (I.sup.3 L)* Bipolar Dynamic RAM," Digest of Technical Papers, 1976, IEEE International Solid-State Circuits Conference Pages 182 and 183, illustrate a merged bipolar dynamic memory cell. (*I.sup.3 L is a registered trademark of Fairchild Camera and Instrument Corporation).